1. Field of the Invention
The present invention relates to a semiconductor device and an integrated circuit. More particularly, the present invention relates to the semiconductor device and the integrated circuit which can configure a function in each of them even after they are manufactured. In addition, the present invention relates to a method of storing function configuration data.
Further, the present invention relates to an integrated circuit which can configure any symmetric function in it and has a selector capability.
Further, the present invention relates to a method of designing an integrated circuit which realizes any function and relates to the integrated circuit.
2. Description of the Related Art
A reconfigurable logic device, typified by FPGA (Field Programmable Gate Array) or PLD (Programmable Logic Device) becomes widely used for various purposes in addition that the scale of it becomes larger.
When the reconfigurable logic device begins to emerge, it is manly used for realizing a device of which the necessary amount is small but many varieties are needed, or for prototyping. However, the reconfigurable logic device, instead of ASIC (Application Specific Integrated Circuit), is often incorporated into an end product now, because FPGA can satisfy desired performance and it can be shipped several months earlier than ASIC.
Further, research and development of a reconfigurable computing system (RCS) starts to be active, wherein, in the reconfigurable computing system, the reconfigurable logic device is used and a hardware configuration can be changed adaptively according to an application. For example, the reconfigurable computing system (RCS) is shown in Toshinori Sueyoshi, “Present Status and Problems of the Reconfigurable Computing Systems—Toward the Computer Evolution—,” Technical Report of IEICE, VLD96-79, CPSY96-91, 1996-12.
In an integrated circuit which configures the reconfigurable logic device like the above mentioned FGPA, parts for reconfiguring a logic include an input/output part (I/O part), a wiring connection part and a logic part. Among these, a configuring method of the logic part includes technical characteristics used for hardware design and manufacturing. Representative configurable logic blocks are an LUT (Look-Up Table) type shown in FIGS. 1A and 1B, a multiplexer-based block type shown in FIGS. 2A and 2B and a programmable logic array (PLA) type shown in FIG. 3.
The LUT type shown in FIGS. 1A and 1B includes memory elements or memory circuits typified by SRAM wherein the memory elements or memory circuits store function configuration data.
In the following, the LUT type will be described in which the SRAM is used for the logic part. Since the logic part is configured by the SRAM, it can be manufactured by a standard CMOS process. In addition, since a logic is realized by data stored in the SRAM, the logic can be rewritten unlimited times in principle. However, large area is required in the chip for realizing a logic of n (n is a positive integer) input variables since 2n SRAMs are necessary. In addition, an external ROM is necessary for storing data continually since data stored in the SRAM disappears when a power supply is stopped.
An SRAM cell which is used for the changeable logic part in the FPGA is usually includes 6 transistors as shown in FIG. 4. Thus, an LUT for k input variables requires 2k SRAMs so that the number of transistors for the SRAMs becomes 6×2k.
In many cases, the number k of input variables of the LUT type FPGA which is generally used is 4 or 5. An LUT of k=4 requires 96 transistors only for the SRAM cells, and an LUT of k=5 requires 192 transistors. In addition, peripheral circuits such as an address decoder, a writing circuit, a pre-charge circuit and a sense amplifier are necessary. Thus, the scale of the circuit becomes large.
As for the multiplexer-based block type shown in FIGS. 2A and 2B, a logic is realized by a multi-stage structure of multiplexers. This multiplexer-based block type also can realize any Boolean function same as the LUT type. However, this type needs a memory element or a memory circuit, other than the multiplexers, for storing function configuration data. As the memory element or memory circuit, an anti-fuse or an 1 bit SRAM or the like is used. Generally, the anti-fuse is often used for realizing fast multi-stage logic operation. However, it is difficult to reconfigure a logic function after a logic function is configured. As for the 1 bit SRAM, in the same way as the LUT type, large area is necessary in a chip since at least 2n SRAMs are required for realizing logics of n input variables.
As for the PLA shown in FIG. 3, a logic is defined by a connection state of an AND array and an OR array on the basis that any Boolean function can be configured by AND and OR. That is, PLA realized a sum-of-products type logic. In each array, memory elements or memory circuits such as anti-fuses, EPROMs, EEPROMs and SRAMs are used for the connection of wiring. Especially, EEPROMs are ofen utilized to realize wired-AND easily.
The anti-fuse has an advantage in that it operates relatively fast. However, there is a problem in that reconfiguration is difficult after a logic is configured once. As for the EPROM or EEPROM, area for this memory element is necessary for storing function configuration data other than circuits for the AND array and the OR array. In addition, generally, a data writing part and/or a data erasing part is necessary for rewriting the function configuration data. Thus, it is difficult to reconfigure a logic function easily and for a short time. Especially, as for the case of the EPROM, since irradiating ultraviolet is necessary for rewriting the logic function, it is not easy to reconfiguring the logic function. As for the EEPROM, the size of the memory cell is larger than that of the EPROM. In addition, tunnel current is used for data writing and data erasing. Thus, it is difficult to perform data writing and data erasing speedily.
Other programmable hardware, in which a logic realizing method may be different, also has the memory element or the memory circuit for storing the function configuration data.
Conventional programmable hardware is considered as a digital signal processing device which uses two-valued data representing logical 1 or 0 as an input/output signal, in which the function configuration data is also stored as two-valued data.
When an advanced programmable hardware is desired, wherein the advanced programmable hardware can process multilevel and/or analog signals as well as the two-valued signals, the conventional method lacks flexibility. In addition, by using a circuit structure which can use multilevel signals and/or analog signals internally, it may be possible to reduce area comparing with the conventional circuit.
As mentioned above, when the SRAM is used for storing the function configuration data, area in the chip becomes large. When the anti-fuse is used, reconfiguration is difficult. As for EPROM and EEPROM, a rewriting specific device becomes necessary so that there is a problem in that reconfiguration is not performed fast. In addition, it lacks flexibility when advanced programmable hardware is desired.
In the following, a description on a symmetric function will be given.
Arithmetic operation circuits are often used in an arithmetic part (data pass part) of a microprocessor (μP) or a digital signal processing processor (DSP), which are representative examples of the logic LSI. The arithmetic operation circuit includes an adding circuit, a subtracting circuit, a multiplying circuit and the like. These arithmetic operation circuits often use a full adder which handles the symmetric function.
The symmetric function is a logic function in which the function value is not changed even when input variables are permutated. For example, the output value of AND of two input variables X1 and X2 is not changed even after the values of X1 and X2 are switched. Examples of the symmetric function are AND, OR, NAND, NOR, XOR and XNOR and the like.
In addition, for the control part of the logic LSI, a circuit which includes a selector capability is often used.
Accordingly, circuits which has the symmetric function capability and circuits which has the selector capability, other than sequential circuits including such as registers and latches, are used with high frequency in the logic LSI.
The LUT type FPGA can represent any Boolean function, but does not have the selector or multiplexer capability. In addition, since the logic which is implemented in the LUT is not always a complex one, the capability for realizing any k input variable logic function is not always necessary.
As mentioned above, a circuit structure which has the symmetric function ability and the selector capability simultaneously is not proposed conventionally.
In terms of improving the function of the RCS so that it realizes not only the symmetric function but also any function, it is desirable to satisfy a condition that the time taken for reconfiguring logic function is short. Among the above-mentioned types, the LUT type which uses a memory circuit like the SRAM, a latch circuit or a circuit like DRAM may satisfy this condition.
Representative examples of the reconfigurable logic device having high rewriting speed are DPGA (Dynamically Programmable Gate Array) and DRLE (Dynamically Reconfigurable Logic Engine) in which the LUTs are configured by latch circuits.
The DPGA is described in Andre DeHon, DPGA-Coupled Microprocessors :Commodity ICs for the Early 21st Century,Proceedings of the IEEE Workshop on FPGAs for Custom Computing Machines, April, 1994. In addition, the DRLE is described in T. Fujii, et al., A Dynamically Reconfigurable Logic Engine with a Multi-Context/Multi-Mode Unified-Cell Architecture, ISSCC99, WA21.3 pp. 360-361, 1999.
However, as for the LUT type, since the truth table is directly implemented in circuits, the changeable logic part which can represent any logic function needs to be provided even when only specific logic functions are used. Thus, the logic part of k input variables needs 2k memory cells for implementation as mentioned above. Therefore, there is a problem in that the area cost of the changeable logic part of the LUT type is high.
In order to solve this problem, a circuit can be considered, in which, a circuit which realizes only symmetric functions which is used frequently in arithmetic operation performed in the arithmetic part (or data pass part), a selector circuit which is often used in the control part, and a circuit which realizes all logic functions complementing the above two circuits are realized in low area cost and combined and implemented.
To combine a plurality of basic functions so as to form a basic unit of the reconfigurable logic device is equivalent to configuring a basic unit from a plurality of LUTS. Generally, the basic unit of the changeable logic part of an actual reconfigurable logic device is configured like this.
In addition, a method is proposed wherein devices having different characteristics are combined so that the basic unit of the changeable logic part is configured. For example, the method is disclosed in A. Kaviani and S. Brown, The Hybrid Field-Programmable Architecture, IEEE Design&Test of Computers, pp. 74-83, April June, 1999.
However, it is difficult for the conventional reconfigurable logic device to realize only special functions having special properties.
It is known that any logic function can be represented by a threshold logic, more specifically, it is known that any logic function can be realized by a multistage structure of threshold elements in which weights and threshold values are adjusted. One of the threshold elements which can realize the threshold logic effectively is a neuron MOS transistor. An example is disclosed in Tadashi Shibata and Tadahiro Ohmi, “A Functional MOS Transistor Featuring Gate-Level Weighted Sum and Threshold Operations,” IEEE Transactions on Electron Devices, Vol.39, No.6, pp.1444-1455, 1992. FIGS. 5A-5C show a structure and a layout of the neuron MOS transistor and a circuit which is called a complementary neuron MOS inverter. The complementary neuron MOS inverter includes two neuron MOS transistors which has different conductivity types. In the following, a complementary MOS inverter which is similar to a standard complementary neuron MOS inverter (CMOS inverter) will be called a neuron MOS inverter.
FIG. 5A shows a layout, FIG. 5B shows a section view of X-X′ in FIG. 5A, and FIG. 5C shows a circuit diagram of an n input complementary neuron MOS inverter.
The neuron MOS transistor has a floating gate in an region between the source region and the drain region and a plurality of input gates which are capacitively coupled to the floating gate as shown in FIGS. 5A and 5B.
FIGS. 6A and 6B show a circuit of a CMOS type inverter (neuron MOS inverter) which uses a conventional neuron MOS transistor, in which FIG. 6A shows the circuit diagram depicted by transistor symbols and FIG. 6B shows the circuit depicted by logical symbols.
In the following, the operation of the inverter, shown in FIGS. 6A and 6B for example, will be described in detail.
Let us assume that Vi is a signal voltage input from ith input terminal in n input terminals, Ci is an input gate capacitance value between the ith input terminal and the floating gate, ΣCnmos+ΣCpmos is the sum total of capacitance values between the floating gate and source, drain, substrate (well) terminals. When the following formula 1 is true,                                                                                           ∑                                      i                    =                    1                                    n                                ⁢                                                                   ⁢                                  C                  i                                            〉                        〉                    ⁢                      ∑                          C              nmos                                      +                  ∑                      C            pmos                                              (                  formula          ⁢                                           ⁢          1                )            the total sum of electrical charge amount Qf which is accumulated in each input gate capacitance is represented by the following formula 2.                               Q          f                =                              ∑                          i              =              1                        n                    ⁢                                    C              i                        ·                          V              i                                                          (                  formula          ⁢                                           ⁢          3                )            
Then, the floating gate voltage Vfg can be represented by the following formula 3, in which Vfg is roughly proportional to Qf.                               V          fg                ~                                            ∑                              i                =                1                            n                        ⁢                                                   ⁢                          (                                                C                  i                                ·                                  V                  i                                            )                                                          ∑                              i                =                1                            n                        ⁢                                                   ⁢                          C              i                                                          (                  formula          ⁢                                           ⁢          3                )            
When the floating gate voltage Vfg is larger than a threshold voltage Vfth with respect to the floating gate, the output signal voltage Vout of the neuron MOS inverter becomes a logically inverted voltage of the floating gate voltage Vfg with respect to the threshold voltage Vfth.
As mentioned above, the neuron MOS inverter is a kind of a threshold element which performs a threshold process. That is, the neuron MOS inverter is a kind of a threshold element which performs a threshold process on the floating gate voltage Vfg by the threshold voltage Vfth, wherein the floating gate voltage Vfg is roughly proportional to Qf which is a result of sum of products of Vi and Ci for all input signals.
In the following, a case where the input signal is a two-valued value will be described.
When assuming that the input signal voltage may take two stable voltages {0, Vdd}, and Ci=C·wi where wi is an input gate capacitance ratio that is normalized Ci by the smallest input gate capacitance value, the total sum Qf of the charge amount accumulated in each input gate capacitance is represented by the following formulas 4 and 5.                               Q          f                =                  C          ⁢                                    ∑                              i                =                1                            N                        ⁢                                          x                i                            ·                              w                i                                                                        (                  formula          ⁢                                           ⁢          4                )                                          x          i                =                                            V              i                                      V                              d                ⁢                                                                   ⁢                d                                              =                      {                                                            1                                                                      for                    ⁢                                                                                   ⁢                                          (                                                                        V                          i                                                =                                                  V                                                      d                            ⁢                                                                                                                   ⁢                            d                                                                                              )                                                                                                                    0                                                                      for                    ⁢                                                                                   ⁢                                          (                                                                        V                          i                                                =                        0                                            )                                                                                                                              (                  formula          ⁢                                           ⁢          5                )            
When assuming that the output signal of the neuron MOS inverter is Vout, a voltage which satisfies Vout≧Vfth is represented as Vhigh, a voltage which satisfies Vout<Vfth is represented as Vlow, the relationship between Vout and Qf is represented by the following formulas 6 and 7.                                           V            fg                    ~                      1                                          ∑                                  i                  =                  1                                n                            ⁢                                                           ⁢                              w                i                                                    ·                  (                                    ∑                              i                =                1                            n                        ⁢                                                   ⁢                                          x                i                            ·                              w                i                                              )                                    (                  formula          ⁢                                           ⁢          6                )                                          V          out                =                  {                                                                                          V                    high                                    ⁢                                                                           ⁢                  for                  ⁢                                                                           ⁢                                      (                                                                  V                        fg                                            <                                              V                        fth                                                              )                                                                                                                                            V                    low                                    ⁢                                                                           ⁢                  for                  ⁢                                                                           ⁢                                      (                                                                  V                        fg                                            ≧                                              V                        fth                                                              )                                                                                                          (                  formula          ⁢                                           ⁢          7                )            
Accordingly, when two-valued values {0, Vdd} are used for input signals, the output signal value of the neuron MOS inverter is decided by the sum of capacitance ratio of the input gate capacitance where xi=1 is input, that is,                     (                              ∑                          i              =              1                        n                    ⁢                                    x              i                        ·                          w              i                                      )                            (                  formula          ⁢                                           ⁢          8                )            and Vfth.
Such a neuron MOS transistor and a basic structure of a circuit using it are disclosed in a Japanese laid open patent applications No. 6-77427 and 7-161942. According to a technique shown in the Japanese laid open patent application No. 6-77427, a logic function of an integrated circuit for realizing Boolean functions is formed by using a mask for forming wiring during manufacturing processes. Therefore, reconfiguration of the logic function after manufacturing is impossible. This is similar to the concept of a gate array.
Therefore, in the Japanese laid open patent application No. 6-77427, after-mentioned ideas of the present invention is not disclosed.
As for a structure disclosed in Japanese laid open patent application No.7-161942, unnecessary charge accumulated in the floating gate is removed by connecting the floating gate to a terminal having a voltage for improving a reliability of the neuron MOS transistor. Thus, in the Japanese laid open patent application No. 7-161942, after-mentioned ideas of the present invention is not disclosed.
In Tadashi Shibata, Koji Kotani and Tadahiro Ohmi, “Real-Time Reconfigurable Logic Circuits Using Neuron MOS Transistors”, IEEE International Solid-State Circuits Conference, FA15.3, pp. 238-239, 1993, it is disclosed that a Boolean function for a specific number of inputs can be represented by using a neuron MOS circuit configured by the neuron MOS transistors. However, signals for selecting a Boolean function is supplied directly from the outside of the integrated circuit. Therefore, this document does not discloses an idea that the neuron MOS circuit holds function or logic configuration data. That is, according to the technique disclosed in this document, the function capability can not be realized unless control signals are provided continuously from the outside.
It is conceivable that to provide a memory device for storing the control signals, which select a Boolean function, for the circuit of the above document. When a volatile memory typified by SRAM is added, as the memory device, to the circuit configured by the neuron MOS inverters regarding process speed as important, this circuit structure is equivalent to a circuit in which an address decoder part of the LUT type FPGA is configured by the neuron MOS inverters. This is not very useful.
In addition, a design method of a symmetric function by using a neuron MOS circuit is disclosed in Kazuo Aoyama, Hiroshi Sawada, Akira Nagoya, Kazuo Nakajima, “A Design Method for a Circuit with Neuron MOS Transistors Realizing,” Technical Report of IEICE, CPSY99-90, PP. 49-51, 1999-11.
Further a basic structure of a neuron MOS transistor is disclosed in a Japanese laid open patent application No. 3-6679. In this document, a capacitance value between an input gate terminal and a floating gate terminal is positioned as a weight coefficient which is described in W. S. McCulloch and W. A. Pitts, “A Logical Calculus of the Ideas Immanent in Neural Nets”, Bull. Match. Biophy., Vol.5, pp. 115-133, 1992, or a weight coefficient for making a D-A (Digital-Analog) converter when the neuron MOS transistor is used for a source follower type circuit.
As mentioned above, there are following problems in the conventional programmable hardware. That is, as for the LUT type, a large area is required for the changeable logic part which consists of memory circuits such as SRAMs in order to enable reconfiguring of a logic function. As for the multiplexer type and the PLA type, the anti-fuse or memory elements such as EEPROMs and EPROMs are required so that reconfiguring the logic function can not be performed easily and in a short time, wherein it is very difficult for the anti-fuse to reconfigure the logic function due to the principle and the EEPROM requires a specific device for data writing and deleting.
Therefore, an integrated circuit is desired wherein the area of memory elements or memory circuit other than main configuration elements is not necessary for realizing the changeable logic part.
A device which can reconfigure the logic function speedily among conventional reconfigurable logic device is the LUT type FPGA, in which the changeable logic part is configured by the LUT including SRAMs. The LUT having k input variables can realize any Boolean function which can be generated by k input variables. However, there is a problem in that a large area is required in the LSI. Thus, a changeable logic part which has small area and can reconfigure the logic function is desired.
In addition, a circuit structure and the designing method are desired, in which a circuit for realizing symmetric function and a small area cost circuit for realizing any function including symmetric functions are combined in the changeable logic part of a neuron MOS circuit.